SK Hynix Says It Will Set HBF Standard in January 2027 to Break AI Bottlenecks

Ahn Hyun: ‘10 Times the Capacity of HBM’

“High-bandwidth flash, or HBF, offers about half the bandwidth of existing high-bandwidth memory, or HBM, but can increase capacity by more than 10 times. We will overcome the memory data-transfer bottleneck driven by surging demand for AI inference.”

Ahn Hyun, president and chief development officer at SK Hynix, presented HBF and 3D-stacked DRAM as next-generation AI memory solutions to overcome the limits of HBM during a keynote speech at Semiconductor Exhibition 2026, or SEDEX 2026, held at Coex in Seoul on Oct. 14.

Ahn said AI infrastructure performance scale will expand 20-fold by 2030 from 2026 levels. With requests for inference services rising sevenfold each year, memory must move beyond being a standalone component and build a new layer to address bottlenecks, he added.

HBF is a next-generation memory technology that stacks NAND flash vertically instead of DRAM and connects the layers with through-silicon vias, or TSV. NAND is slower than DRAM and has limits on write endurance, but in AI inference, read workloads outnumber writes by hundreds of thousands of times.

SK Hynix said it applied prefetch technology to offset NAND’s speed limitations by pulling in data in advance. The company plans to finalize the technical standard in January 2027 and build an ecosystem around it.

Another key technology SK Hynix presented was 3D-stacked DRAM, which places DRAM directly on top of graphics processing units, or GPUs, or neural processing units, or NPUs. The approach reduces the distance data must travel compared with existing HBM.

Separately, China’s ChangXin Memory Technologies, or CXMT, has signaled it will adopt 4F², a next-generation server DRAM technology, while Samsung Electronics said it is also developing the technology. Asked about the development progress on Oct. 14, Song Jae-hyuk, Samsung’s chief technology officer and president, said, “We’re working hard on it.”

4F² is a measure of the area occupied by a single DRAM cell. Compared with the existing 6F² structure, the next-generation technology can reduce cell area by about one-third.

Roh Yoo-jung and Won Jong-hwan, Hankyung.com reporters yjroh@hankyung.com